𝔖 Bobbio Scriptorium
✦   LIBER   ✦

A new soft-error-immune DRAM cell using a stacked CMOS structure

✍ Scribed by Terada, K.; Kurosawa, S.; Takeshima, T.

Book ID
114596014
Publisher
IEEE
Year
1987
Tongue
English
Weight
628 KB
Volume
34
Category
Article
ISSN
0018-9383

No coin nor oath required. For personal study only.

πŸ“œ SIMILAR VOLUMES

A new soft-error-immune DRAM cell using
A new soft-error-immune DRAM cell using a stacked CMOS structure: K Tereda, S Kurosawa, T Takeshima (NEC Corp., Kawasaki, Japan) IEEE Trans. Electron. Devices (USA), vol. ED-34, no. 6, pp. 1368–1372 (June 1987)
πŸ“‚ Article πŸ“… 1988 πŸ› Elsevier Science 🌐 English βš– 72 KB

A VLSI memory cell is proposed that offers high immunity to alpha-particle-induced soft errors and a cell area comparable to a one-transistor memory cell. This memory cell consists of a pair of complementary MOSFETs and one capacitor. The PMOSFET is formed in an SOI film over the NMOSFET. Since both

A 5-bit CMOS phase shifter with low phas
A 5-bit CMOS phase shifter with low phase and amplitude error using a new 180Β° phase shifter featuring process-variation immunity
✍ Dong-Woo Kang; Songcheol Hong πŸ“‚ Article πŸ“… 2010 πŸ› John Wiley and Sons 🌐 English βš– 589 KB

## Abstract In this letter, a high‐performance 5‐bit CMOS phase shifter using a newly proposed 180Β° bit is presented for a Ku‐band mobile satellite phased array receiver. The 180Β° phase shifter exhibits good tolerance to substrate parasitic capacitances when compared with a conventional high‐pass/l