A new soft-error-immune DRAM cell using a stacked CMOS structure: K Tereda, S Kurosawa, T Takeshima (NEC Corp., Kawasaki, Japan) IEEE Trans. Electron. Devices (USA), vol. ED-34, no. 6, pp. 1368–1372 (June 1987)
- Book ID
- 104157682
- Publisher
- Elsevier Science
- Year
- 1988
- Tongue
- English
- Weight
- 72 KB
- Volume
- 19
- Category
- Article
- ISSN
- 0026-2692
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✦ Synopsis
A VLSI memory cell is proposed that offers high immunity to alpha-particle-induced soft errors and a cell area comparable to a one-transistor memory cell. This memory cell consists of a pair of complementary MOSFETs and one capacitor. The PMOSFET is formed in an SOI film over the NMOSFET. Since both storage capacitor nodes are kept electrically floating in retention periods and one storage capacitor node is formed in a thin SOl film, an alpha-particle hit does not destroy the stored charge of this memory cell. It is sufficient for an SOI-PMOSFET to provide only three orders ofmagnitude on/offcurrent ratio. Experimental memory cells were fabricated using polysilicon film as an SOI film. Measurements confirm the main effectiveness of this memory cell. (6 refs.