✦ LIBER ✦

A Markov chain-based yield formula for VLSI fault-tolerant chips

✍ Scribed by Ciciani, B.; Iazeolla, G.

Book ID: 119778303
Publisher: IEEE
Year: 1991
Tongue: English
Weight: 841 KB
Volume: 10
Category: Article
ISSN: 0278-0070
DOI: 10.1109/43.68412

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design considerations for a single-chip

Design considerations for a single-chip fault tolerant VLSI microprocessor

✍ Goode, A.J. 📂 Article 📅 1985 🏛 Institution of Electrical Engineers ⚖ 944 KB

A reconfigurable and adaptive routing me

A reconfigurable and adaptive routing method for fault-tolerant mesh-based networks-on-chip

✍ Mojtaba Valinataj; Siamak Mohammadi; Juha Plosila; Pasi Liljeberg; Hannu Tenhune 📂 Article 📅 2011 🏛 Elsevier Science 🌐 English ⚖ 715 KB

A class of iteration methods based on th

A class of iteration methods based on the moser formula for nonlinear equations in Markov chains

✍ Zhong-Zhi Bai 📂 Article 📅 1997 🏛 Elsevier Science 🌐 English ⚖ 945 KB

Many stochastic models in queueing, inventory, communications, and dam theories, etc., result in the problem of numerically determining the minimal nonnegative solutions for a class of nonlinear matrix equations. Various iterative methods have been proposed to determine the matrices of interest. We

[IEEE 2010 IEEE International Symposium

[IEEE 2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Kyoto, Japan (2010.10.6-2010.10.8)] 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems - Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip

✍ MacLean, E.; Jain, V. K. 📂 Article 📅 2010 🏛 IEEE ⚖ 672 KB

[IEEE 2010 IEEE International Symposium

[IEEE 2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Kyoto, Japan (2010.10.6-2010.10.8)] 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems - A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip

✍ Chan, Min-Ju; Hsu, Chun-Lung 📂 Article 📅 2010 🏛 IEEE ⚖ 411 KB

[IEEE Comput. Soc 20th IEEE Internationa

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Software-based self-test for pipelined processors: a case study

✍ Hatzimihail, M.; Xenoulis, G.; Psarakis, M.; Gizopoulos, D.; Paschalis, A. 📂 Article 📅 2005 🏛 IEEE Comput. Soc ⚖ 356 KB