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[IEEE 2010 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Kyoto, Japan (2010.10.6-2010.10.8)] 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems - A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip

✍ Scribed by Chan, Min-Ju; Hsu, Chun-Lung

Book ID: 120165349
Publisher: IEEE
Year: 2010
Weight: 411 KB
Category: Article
ISBN: 1424484472
DOI: 10.1109/DFT.2010.21

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