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A generalized fault simulator for combinational logic circuits

โœ Scribed by Rajesh Raina; T.N. Rajashekhara


Book ID
113211884
Publisher
Elsevier Science
Year
1989
Tongue
English
Weight
409 KB
Volume
15
Category
Article
ISSN
0045-7906

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An algorithm for stuck-at fault coverage
โœ Leonard J. Tung ๐Ÿ“‚ Article ๐Ÿ“… 1989 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 726 KB

An algorithm for stuck-at fault coverage analysis of digital logic circuits is presented. Based on a recently developed stuck-at fault model, the algorithm determines the effectiveness of a given test input set. The algorithm is applicable for studying sequential logic circuits, as well as combinati