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0.5-μm 2 M-transistor BiPNMOS channelless gate array

✍ Scribed by Hara, H.; Sakurai, T.; Noda, M.; Nagamatsu, T.; Seta, K.; Momose, H.; Niitsu, Y.; Miyakawa, H.; Watanabe, Y.

No coin nor oath required. For personal study only.

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