𝔖 Bobbio Scriptorium
✦   LIBER   ✦

Wafer level chip scale packaging


Publisher
Elsevier Science
Year
2004
Tongue
English
Weight
47 KB
Volume
17
Category
Article
ISSN
0961-1290

No coin nor oath required. For personal study only.


πŸ“œ SIMILAR VOLUMES


Pirani pressure sensor for smart wafer-l
✍ F. Mailly; N. Dumas; N. Pous; L. Latorre; O. Garel; E. Martincic; F. Verjus; C. πŸ“‚ Article πŸ“… 2009 πŸ› Elsevier Science 🌐 English βš– 911 KB

Systems in Package (SiP) contain an increasing number of MEMS components such as resonators for time references or RF filtering. These resonators are packaged at wafer level and the cavity quality has to be guaranteed in terms of pressure and moisture level by the final manufacturing test. Therefore

Laser decapsulation of molding compound
✍ H. Qiu; H.Y. Zheng; X.C. Wang; G.C. Lim πŸ“‚ Article πŸ“… 2005 πŸ› Elsevier Science 🌐 English βš– 628 KB

A potential laser etching method has been investigated and implemented in decapsulating wafer level chip size package (WLCSP). A chemically and physically clean surface could be obtained and lead to successful solder reflowing. Firstly, fast and cost-saving transfer molding was suggested to replace

Characterization and lumped circuit mode
✍ Young Seek Cho; Rhonda Franklin Drayton πŸ“‚ Article πŸ“… 2009 πŸ› John Wiley and Sons 🌐 English βš– 488 KB

## Abstract An ultra‐wideband flip‐chip transition is proposed for wafer level packaging applications. The locally matched flip‐chip scheme has an air cavity underneath a flip‐chip die and local trenches in the flip‐chip bond pad area to provide matching. The measured response up to 110 GHz has a r