✦ LIBER ✦

URPR-1: A single-chip VLIW architecture

✍ Scribed by Bogong Su; Jian Wang; Zhizhong Tang; Cihong Zhang; Wei Zhao

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Rigel: A 1,024-Core Single-Chip Accelera

✍ Johnson, D.R.; Johnson, M.R.; Kelm, J.H.; Tuohy, W.; Lumetta, S.S.; Patel, S.J. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 304 KB

Design of a VLIW architecture constructe

✍ Peter Pfahler; Christof Nagel; Franz-Josef Rammig; Uwe Kastens 📂 Article 📅 1993 🏛 Elsevier Science ⚖ 664 KB

Architectural design and realization of

✍ Marc Biver; Hubert Kaeslin; Carlo Tommasini 📂 Article 📅 1989 🏛 Elsevier Science 🌐 English ⚖ 810 KB

A single chip MPEG1 decoder

✍ Kawahara, K.; Yamauchi, H.; Okada, S. 📂 Article 📅 1995 🏛 IEEE 🌐 English ⚖ 640 KB

A 1-GHz single-chip quadrature modulator

✍ Steyaert, M.; Roovers, R. 📂 Article 📅 1992 🏛 IEEE 🌐 English ⚖ 395 KB

A 1.71-million transistor CMOS CPU chip

✍ Saito, Y.; Shimazu, Y.; Shimizu, T.; Shirai, K.; Fujioka, I.; Nishiwaki, Y.; Hin 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 735 KB