Sequential circuit test generation by re
β
Kazunori Hikone; Mitsuji Ikeda; Kazumi Hatayama; Terumine Hayashi
π
Article
π
1993
π
John Wiley and Sons
π
English
β 921 KB
## Abstract This paper presents a test generation method using an optimization technique for a single stuckβat fault in synchronous sequential circuits. This method utilizes a new real number simulation for defining the cost of an input pattern for a given fault and leads an input pattern to a test