✦ LIBER ✦

Theorems for identifying undetectable faults in partial-scan circuits

✍ Scribed by Pomeranz, I.; Reddy, S.M.

Book ID: 118698418
Publisher: IEEE
Year: 2003
Tongue: English
Weight: 326 KB
Volume: 22
Category: Article
ISSN: 0278-0070
DOI: 10.1109/tcad.2003.814957

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

On Clustering of Undetectable Single Stu

On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits

✍ Pomeranz, I.; Reddy, S.M. 📂 Article 📅 2010 🏛 IEEE 🌐 English ⚖ 288 KB

Theorems for Fault Collapsing in Combina

Theorems for Fault Collapsing in Combinational Circuits

✍ Audhild Vaaje 📂 Article 📅 2006 🏛 Springer US 🌐 English ⚖ 290 KB

Input Necessary Assignments for Testing

Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits

✍ Pomeranz, I.; Reddy, S.M. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 245 KB

Design-for-testability to achieve comple

Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits

✍ Irith Pomeranz; Sudhakar M. Reddy 📂 Article 📅 2001 🏛 Elsevier Science 🌐 English ⚖ 207 KB

We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modi®cations to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and p

Test Strength: A Quality Metric for Tran

Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits

✍ Pomeranz, I.; Reddy, S.M. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 212 KB