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The logic design language and verification environment for the VLSI-/370

โœ Scribed by Wolfgang Roesner


Publisher
Elsevier Science
Year
1988
Weight
624 KB
Volume
24
Category
Article
ISSN
0165-6074

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A novel output stage design for four-phase rstioless dynamic logic is proposed for a low speed asynchronous pump circuit. The main features of the proposed circuit are that the precharge capacitance is reduced significantly, leading to lower power consumption, and the circuit can operate in the sync