𝔖 Bobbio Scriptorium
✦   LIBER   ✦

Testability and test compaction for decision diagram circuits

✍ Scribed by Bystrov, A.; Almaini, A.E.A.

Book ID
114447727
Publisher
The Institution of Electrical Engineers
Year
1999
Tongue
English
Weight
648 KB
Volume
146
Category
Article
ISSN
1350-2409

No coin nor oath required. For personal study only.

πŸ“œ SIMILAR VOLUMES

Test compaction for sequential circuits
Test compaction for sequential circuits
✍ Niermann, T.M.; Roy, R.K.; Patel, J.H.; Abraham, J.A. πŸ“‚ Article πŸ“… 1992 πŸ› IEEE 🌐 English βš– 766 KB
Combined probabilistic testability calcu
Combined probabilistic testability calculation and compact test generation for PLAs
✍ BjΓΈrg Reppen; Einar J. Aas πŸ“‚ Article πŸ“… 1991 πŸ› Springer US 🌐 English βš– 1017 KB

PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability

Test and Design-for-Testability in Mixed
Test and Design-for-Testability in Mixed-Signal Integrated Circuits || Introduction
✍ Huertas, JosΓ© L. πŸ“‚ Article πŸ“… 2004 πŸ› Springer US 🌐 English βš– 665 KB

Test and Design-for-Testability in Mixed-Signal Integrated Circuits deals with test and design for test of analog and mixed-signal integrated circuits. Especially in System-on-Chip (SoC), where different technologies are intertwined (analog, digital, sensors, RF); test is becoming a true bottleneck