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Test pattern generation and clock disabling for simultaneous test time and power reduction

✍ Scribed by Jih-Jeen Chen; Chia-Kai Yang; Kuen-Jong Lee

Book ID: 118698350
Publisher: IEEE
Year: 2003
Tongue: English
Weight: 687 KB
Volume: 22
Category: Article
ISSN: 0278-0070
DOI: 10.1109/tcad.2002.807890

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