Test cost reduction for logic circuits: Reduction of test data volume and test application time

✍ Scribed by Yoshinobu Higami; Seiji Kajihara; Hideyuki Ichihara; Yuzo Takamatsu

• Publisher: John Wiley and Sons
• Year: 2005
• Tongue: English
• Weight: 347 KB
• Volume: 36
• Category: Article
• ISSN: 0882-1666
• DOI: 10.1002/scj.20240

✦ Synopsis

Abstract

We believe that reduction of the testing cost is becoming increasingly important as the size of VLSIs becomes larger. Moreover, as the structure of VLSIs becomes more complicated, test compaction, test compression, and test application time reduction for non‐stuck‐at faults, such as delay faults, bridging faults, crosstalk faults, and open faults, must be considered. In addition, new methods of fault diagnosis and high‐level testing must be developed in order to reduce testing costs or diagnostic costs. In this paper we have surveyed recent research on the reduction of testing cost for logic circuits, including test compaction for combinational circuits and sequential circuits, test compaction under IDDQ testing, and test compression and test application time reduction for scan circuits. © 2005 Wiley Periodicals, Inc. Syst Comp Jpn, 36(6): 69–83, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.20240