✦ LIBER ✦

System-level performance analysis for designing on-chip communication architectures

✍ Scribed by Lahiri, K.; Raghunathan, A.; Dey, S.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design space exploration for optimizing

✍ Lahiri, K.; Raghunathan, A.; Dey, S. 📂 Article 📅 2004 🏛 IEEE 🌐 English ⚖ 549 KB

System Level Design for System on a Chip

✍ W. Shields Neely; Vincent John Mooney 📂 Article 📅 1998 🏛 Springer US 🌐 English ⚖ 86 KB

Design methodology for on-chip bus archi

✍ Lee, J. 📂 Article 📅 2012 🏛 The Institution of Engineering and Technology 🌐 English ⚖ 720 KB

System-on-a-chip design for modern commu

✍ Chou, E.Y.; Bing Sheu 📂 Article 📅 2001 🏛 IEEE 🌐 English ⚖ 275 KB

MIMO Architecture for Coherent Optical W

✍ Niu, Mingbo; Cheng, Julian; Holzman, Jonathan F. 📂 Article 📅 2013 🏛 The Optical Society 🌐 English ⚖ 473 KB

System-on-chip communication architectur

✍ Wang, N.; Bayoumi, M.A. 📂 Article 📅 2007 🏛 The Institution of Engineering and Technology 🌐 English ⚖ 345 KB