Switch-Level Timing Simulation of MOS VLSI Circuits
β Scribed by Vasant B. Rao, David V. Overhauser, Timothy N. Trick, Ibrahim N. Hajj
- Publisher
- Springer, Berlin
- Year
- 1989
- Tongue
- English
- Leaves
- 155
- Series
- VLSI, Computer Architecture, and Digital Signal Processing
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
π SIMILAR VOLUMES
<span>Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user fri
<p>P. Antognetti University of Genova, Italy Director of the NATO ASI The key importance of VLSI circuits is shown by the national efforts in this field taking place in several countries at differΒ ent levels (government agencies, private industries, defense deΒ partments). As a result of the evolut
<p>As the complexity and the density of VLSI chips increase with shrinking design rules, the evaluation of long-term reliability of MOS VLSI circuits is becoming an important problem. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis
<p>Circuit simulation has been a topic of great interest to the integrated circuit design community for many years. It is a difficult, and interesting, problem beΒ cause circuit simulators are very heavily used, consuming thousands of computer hours every year, and therefore the algorithms must be v