✦ LIBER ✦

Substrate bias effects on transiently triggered latchup in bulk CMOS

✍ Scribed by Chang, L.; Berg, J.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Layout and bias considerations for preve

✍ Troutman, R.R.; Zappe, H.P. 📂 Article 📅 1984 🏛 IEEE 🌐 English ⚖ 726 KB

The effect of layout, substrate/well bia

✍ Yeu-Haw Yang; Chung-Yu Wu 📂 Article 📅 1989 🏛 Elsevier Science 🌐 English ⚖ 921 KB

Transient latchup in bulk CMOS with a vo

✍ Fu, K.Y. 📂 Article 📅 1985 🏛 IEEE 🌐 English ⚖ 456 KB

Effect of Transistor Density and Charge

✍ Atkinson, Nicholas M.; Ahlbin, Jonathan R.; Witulski, Arthur F.; Gaspard, Nelson 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 834 KB

The Effect of Layout Topology on Single-

✍ Ahlbin, J. R.; Gadlage, M. J.; Ball, D. R.; Witulski, A. W.; Bhuva, B. L.; Reed, 📂 Article 📅 2010 🏛 IEEE 🌐 English ⚖ 657 KB