✦ LIBER ✦

Sub-50 nm gate length SOI transistor development for high performance microprocessors

✍ Scribed by M. Horstmann; D. Greenlaw; Th. Feudel; A. Wei; K. Frohberg; G. Burbach; M. Gerhardt; M. Lenski; R. Stephan; K. Wieczorek; M. Schaller; J. Hohage; H. Ruelke; J. Klais; P. Huebler; S. Luning; R. van Bentum; G. Grasshoff; C. Schwan; J. Cheek; J. Buller; S. Krishnan; M. Raab; N. Kepler

Book ID: 108215107
Publisher: Elsevier Science
Year: 2004
Tongue: English
Weight: 571 KB
Volume: 114-115
Category: Article
ISSN: 0921-5107
DOI: 10.1016/j.mseb.2004.07.077

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Temperature scaling for 35 nm gate

Temperature scaling for 35 nm gate length high-performance CMOS

✍ Th. Feudel; M. Horstmann; M. Gerhardt; M. Herden; L. Herrmann; D. Gehre; Ch. Kru 📂 Article 📅 2004 🏛 Elsevier Science 🌐 English ⚖ 579 KB

Processing of 50 nm gate-length hyd

Processing of 50 nm gate-length hydrogen terminated diamond FETs for high frequency and high power applications

✍ D.A.J. Moran; D.A. MacLaren; S. Porro; H. McLelland; P. John; J.I.B. Wilson 📂 Article 📅 2011 🏛 Elsevier Science 🌐 English ⚖ 466 KB

Sub-50&#xa0;nm gate length SOI transistor development for high performance microprocessors

Sub-50 nm gate length SOI transistor development for high performance microprocessors