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Studies of the quality of GdSiO–Si interface

✍ Scribed by Marcin Iwanowicz; Jakub Jasiński; Grzegorz Głuszko; Lidia Łukasiak; Andrzej Jakubowski; Heinrich Gottlob; Mathias Schmidt

Publisher
Elsevier Science
Year
2011
Tongue
English
Weight
580 KB
Volume
51
Category
Article
ISSN
0026-2714

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✦ Synopsis

In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods (C-V, I-V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C-V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.

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