A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component
Stuck-at-fault testing for quasi-delay-insensitive logic circuits
โ Scribed by Arthit Thongtak; Takashi Nanya
- Publisher
- John Wiley and Sons
- Year
- 1998
- Tongue
- English
- Weight
- 186 KB
- Volume
- 29
- Category
- Article
- ISSN
- 0882-1666
No coin nor oath required. For personal study only.
โฆ Synopsis
In Quasi-Delay-Insensitive (QDI) circuits, some single stuck-at-faults may cause run-away transitions without stopping normal transitions. This paper clarifies problems in detecting such stuck-at-faults and proposes a method for generating test sequences for these problems. In this method, a test sequence is generated by searching for faulty excitation in a specified state transition series and by using a stable condition confirmed by an 8-value logic simulation. This paper also describes a method of using additional test terminals for control and observation signals specified in terms of the logic simulation to find otherwise undetectable faults. The effectiveness of the proposed method is experimentally confirmed by using a benchmark circuit.
๐ SIMILAR VOLUMES
An algorithm for stuck-at fault coverage analysis of digital logic circuits is presented. Based on a recently developed stuck-at fault model, the algorithm determines the effectiveness of a given test input set. The algorithm is applicable for studying sequential logic circuits, as well as combinati