Abstract
This letter presents the implementation technique to reduce circuit area in designing 2.4 GHz CMOS lowโnoise amplifier (LNA) using size efficient inductors. We applied a vertically shunt (M6/M5) and a 3โD helical inductor to input and output matching network to obtain low noise figure and to save silicon area, simultaneously. Because these inductors have smaller area occupation, overall Si area was reduced. Moreover, the feedback capacitor, C~f~ is used to compensate the gain degradation from the high resistive 3โD helical inductor at the LNA output stage. The proposed LNA has a gain of 12.5 dB, noise figure (NF) of 2.72 dB, and โ5 dBm IIP3, whereas dissipating 5.3 mA from 1.5 V supply. Without any degradation in terms of circuit performance, the size of proposed LNA is reduced by 49.5% compared with that using the conventional asymmetric inductors. For low cost, the LNA has been fabricated using a 0.18 ฮผm mixedโsignal CMOS process with top metal thickness of 0.84 ฮผm. ยฉ 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2304โ2308, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24600