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Self-checking CMOS circuits using pass-transistor logic

โœ Scribed by Kanji Hirabayashi


Book ID
104635084
Publisher
Springer US
Year
1991
Tongue
English
Weight
193 KB
Volume
2
Category
Article
ISSN
0923-8174

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โœฆ Synopsis


This article presents a new approach to implementing self-checking circuits in CMOS technology. Implementations are made self-checking with respect to a single line stuck-at 0/1 fault. It is assumed that stuck faults at a common gate of neighboring PMOS and NMOS are not independent and the contact between a PMOS (NMOS) source and a power (ground) line is fault free. Self-checking error checkers for parity, two-rail code, and m-out-ofn code are designed using pass-transistor logic and then verified by fault simulation.


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Differential and pass-transistor CMOS lo
โœ Vojin G. Oklobdzija ๐Ÿ“‚ Article ๐Ÿ“… 1998 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 668 KB

This paper presents a review of differential and pass-transistor logic used in today's high performance systems. Various circuit and logic design styles used in contemporary high performance processors have been reviewed. The new logic is advantageous over standard CMOS in terms of performance and v