Robust SRAM Designs and Analysis

✍ Scribed by Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan (auth.)

• Publisher: Springer-Verlag New York
• Year: 2013
• Tongue: English
• Leaves: 175
• Edition: 1
• Category: Library

✦ Synopsis

This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design.

• Provides a complete and concise introduction to SRAM bitcell design and analysis;
• Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis;
• Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices;
• Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.

✦ Table of Contents

Front Matter....Pages i-xi
Introduction to SRAM....Pages 1-29
Design Metrics of SRAM Bitcell....Pages 31-56
Single-Ended SRAM Bitcell Design....Pages 57-82
2-Port SRAM Bitcell Design....Pages 83-111
SRAM Bitcell Design Using Unidirectional Devices....Pages 113-136
NBTI and Its Effect on SRAM....Pages 137-155
Back Matter....Pages 157-166

✦ Subjects

Circuits and Systems; Electronics and Microelectronics, Instrumentation; Nanotechnology and Microengineering