CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

✍ Scribed by Andrei Pavlov

Publisher: Springer
Year: 2008
Tongue: English
Leaves: 203
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.

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