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Reducing correlation to improve coverage of delay faults in scan-path design

โœ Scribed by Weiwei Mao; Ciletti, M.D.


Book ID
119777775
Publisher
IEEE
Year
1994
Tongue
English
Weight
710 KB
Volume
13
Category
Article
ISSN
0278-0070

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We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modiยฎcations to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and p