A restructurable (reconfigurable) parallel VLSI processor designed to minimize the operation delay time which can be generally used for various operations necessary for controlling an intelligent robot was proposed previously by the authors. This processor is constructed by connecting a number of pr
Reconfigurable parallel VLSI processor for dynamic control of intelligent robots
โ Scribed by Fujioka, Y.; Kameyama, M.; Tomabechi, N.
- Book ID
- 114448225
- Publisher
- The Institution of Electrical Engineers
- Year
- 1996
- Tongue
- English
- Weight
- 721 KB
- Volume
- 143
- Category
- Article
- ISSN
- 1350-2387
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