Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units

✍ Scribed by Yoshichika Fujioka; Nobuhiro Tomabechi

• Publisher: John Wiley and Sons
• Year: 2000
• Tongue: English
• Weight: 254 KB
• Volume: 31
• Category: Article
• ISSN: 0882-1666
• DOI: 10.1002/1520-684x(20001115)31:12<33::aid-scj4>3.0.co;2-3

✦ Synopsis

A restructurable (reconfigurable) parallel VLSI processor designed to minimize the operation delay time which can be generally used for various operations necessary for controlling an intelligent robot was proposed previously by the authors. This processor is constructed by connecting a number of processor elements (PEs) in parallel under the assumption that one PE is integrated with one VLSI chip. In contrast to this, a method for constructing a highly integrated processor by integrating several tens to 100 PEs on a single WSI is investigated in this paper. First, a method for constructing multiple buses efficiently which move a multiple number of integrated PEs effectively is proposed. In addition, a method for constructing a defectsalvaging system utilizing the restructurable parallel architecture by incorporating a defect-salvaging configuration as a measure against the yield decrease of WSI is proposed. As a result of designing a restructurable parallel processor based on the methods proposed, it has been clarified that a WSI scale highly integrated processor with 102 PEs piled up can be constructed with only 35% of the chip surface increase with the incorporation of the defect-salvaging configuration.