Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture

✍ Scribed by Yoshichika Fujioka; Michitaka Kameyama

• Publisher: John Wiley and Sons
• Year: 1999
• Tongue: English
• Weight: 339 KB
• Volume: 30
• Category: Article
• ISSN: 0882-1666
• DOI: 10.1002/(sici)1520-684x(19991115)30:12<43::aid-scj5>3.0.co;2-y

✦ Synopsis

In realization of intelligent robots with the capability of quick response to altering environments, it is necessary to reduce the operation delay time of the sensor input signal to the control output. In this article, dynamically reconfigurable multioperand multiplication-addition based on bit-serial operations on multiple inputs is proposed. As a consequence, not only the utilization of the full address provided in the computational section, but also those of the local memory, controller, and distribution lines inside the chip, can thoroughly be improved. The structure of the corresponding reconfigurable VLSI processor is also proposed. In reconfigurable VLSI processors, the overhead of data transfer between processing elements (PE) is remarkably decreased, resulting in the reduction of the product of the PE chip area and the multiplication-addition time (i.e., areatime product). Therefore, the overall computation capability of the processor is remarkably improved. For example, performance evaluation of the chip based on the 0.8-Pm CMOS design rule showed that the delay time of multioperand multiplications-additions and the areatime product are reduced threefold, compared with those of reconfigurable VLSI processors based on bit-parallel architecture.