Delay fault models for VLSI circuits
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Irith Pomeranz; Sudhakar M Reddy
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Article
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1998
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Elsevier Science
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English
β 218 KB
State-of-the-art technologies for VLSI circuits give rise to various defect mechanisms that may cause a circuit to fail when operated at its designated speed of operation. Such defects are conventionally modeled by delay faults. In this paper, we review delay fault models used for circuits described