This paper looks at the power-performance implications of running parallel applications on chip multiprocessors (CMPs). First, we develop an analytical model that, for the first time, puts together parallel efficiency, granularity of parallelism, and voltage/frequency scaling, to establish a formal
✦ LIBER ✦
Power-performance considerations of parallel computing on chip multiprocessors
✍ Scribed by Li, Jian; Martínez, José F.
- Book ID
- 120689151
- Publisher
- Association for Computing Machinery
- Year
- 2005
- Tongue
- English
- Weight
- 553 KB
- Volume
- 2
- Category
- Article
- ISSN
- 1544-3566
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## Abstract Recent semiconductor technology has made on‐chip multiprocessors with several CPUs and cache memories on a single chip a realistic possibility. Generally, conventional multiprocessor systems with shared memory offer a simple programming model, but need a cache coherency mechanism that m