Power-constrained Testing of VLSI Circuits

✍ Scribed by Nicola Nicolici, Bashir M. Al-Hashimi (auth.)

Publisher: Springer US
Year: 2004
Tongue: English
Leaves: 181
Series: Frontiers in Electronic Testing 22B
Edition: 1
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.

Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

✦ Table of Contents

Design and Test of Digital Integrated Circuits....Pages 1-20
Power Dissipation During Test....Pages 21-30
Approaches to Handle Test Power....Pages 31-49
Power Minimization Based on Best Primary Input Change Time....Pages 51-85
Test Power Minimization Using Multiple Scan Chains....Pages 87-112
Power-conscious Test Synthesis and Scheduling....Pages 113-137
Power Profile Manipulation....Pages 139-157
Conclusion....Pages 159-161

✦ Subjects

Circuits and Systems; Electronic and Computer Engineering; Computer-Aided Engineering (CAD, CAE) and Design

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