Photonic Network-on-Chip Design
โ Scribed by Keren Bergman, Luca P. Carloni, Aleksandr Biberman, Johnnie Chan, Gilbert Hendry (auth.)
- Publisher
- Springer-Verlag New York
- Year
- 2014
- Tongue
- English
- Leaves
- 220
- Series
- Integrated Circuits and Systems 68
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
โฆ Synopsis
This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting the reader with all the issues in the design space, the discussion concludes with design automation techniques, supplemented by provided software.
โฆ Table of Contents
Front Matter....Pages i-x
Introduction....Pages 1-9
Photonic Interconnects....Pages 11-26
Silicon Photonics....Pages 27-78
Photonic Simulation and Design Space....Pages 79-99
Photonic Network Architectures I: Circuit Switching....Pages 101-164
Photonic Network Architectures II: Wavelength Arbitration and Routing....Pages 165-172
Photonic Network Architectures III: Advanced Photonic Architectures....Pages 173-202
Conclusions....Pages 203-205
Back Matter....Pages 207-213
โฆ Subjects
Circuits and Systems;Microwaves, RF and Optical Engineering;Optics and Electrodynamics
๐ SIMILAR VOLUMES
<p>From basic architecture, interconnection, and parallelization to power optimization, this book provides a comprehensive description of emerging multicore systems-on-chip (MCSoCs) hardware and software design. Highlighting both fundamentals and advanced software and hardware design, it can serve a
<p><P>Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another
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