Designing Reliable and Efficient Networks on Chips

✍ Scribed by Dr. Srinivasan Murali (auth.)

• Publisher: Springer Netherlands
• Year: 2009
• Tongue: English
• Leaves: 200
• Series: Lecture Notes in Electrical Engineering 34
• Edition: 1
• Category: Library

✦ Synopsis

Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

✦ Table of Contents

Front Matter....Pages i-x
Introduction....Pages 1-12
Front Matter....Pages 12-12
Designing Crossbar Based Systems....Pages 15-37
Netchip Tool Flow for NoC Design....Pages 39-42
Designing Standard Topologies....Pages 43-56
Designing Custom Topologies....Pages 57-75
Supporting Multiple Applications....Pages 77-93
Supporting Dynamic Application Patterns....Pages 95-113
Front Matter....Pages 115-115
Timing-Error Tolerant NoC Design....Pages 117-139
Analysis of NoC Error Recovery Schemes....Pages 141-152
Fault-Tolerant Route Generation....Pages 153-167
NoC Support for Reliable On-Chip Memories....Pages 169-186
Conclusions and Future Directions....Pages 187-189
Back Matter....Pages 191-198

✦ Subjects

Circuits and Systems; Processor Architectures