Network-on-Chip Architectures: A Holistic Design Exploration

✍ Scribed by Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das (auth.)

Publisher: Springer Netherlands
Year: 2010
Tongue: English
Leaves: 235
Series: Lecture Notes in Electrical Engineering 45
Edition: 1
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.

✦ Table of Contents

Front Matter....Pages i-xxi
Front Matter....Pages 18-18
Introduction....Pages 1-12
A Baseline NoC Architecture....Pages 13-16
ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers [39]....Pages 19-40
RoCo: The Row–Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks [40]....Pages 41-64
Exploring FaultoTolerant Network-on-Chip Architectures [37]....Pages 65-92
On the Effects of Process Variation in Network-on-Chip Architectures [45]....Pages 93-115
Front Matter....Pages 118-118
The Quest for Scalable On-Chip Interconnection Networks: Bus/NoC Hybridization [15]....Pages 119-146
Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem) [43]....Pages 147-170
A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures [44]....Pages 171-197
Digest of Additional NoC MACRO-Architectural Research....Pages 199-205
Conclusions and Future Work....Pages 207-209
Back Matter....Pages 211-223

✦ Subjects

Circuits and Systems; Processor Architectures

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