Designing 2D and 3D Network-on-Chip Architectures

✍ Scribed by Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Axel Jantsch (auth.)

Publisher: Springer-Verlag New York
Year: 2014
Tongue: English
Leaves: 271
Edition: 1
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

✦ Table of Contents

Front Matter....Pages i-xiii
Front Matter....Pages 1-1
Network-on-Chip Technology: A Paradigm Shift....Pages 3-18
NoC Modeling and Topology Exploration....Pages 19-49
Communication Architecture....Pages 51-96
Power and Thermal Effects and Management....Pages 97-126
NoC-Based System Integration....Pages 127-145
NoC Verification and Testing....Pages 147-159
The Spidergon STNoC....Pages 161-190
Middleware Memory Management in NoC....Pages 191-208
On Designing 3-D Platforms....Pages 209-236
The SYSMANTIC NoC Design and Prototyping Framework....Pages 237-255
Front Matter....Pages 257-257
Projects on Network-on-Chip....Pages 259-265

✦ Subjects

Circuits and Systems; Electronics and Microelectronics, Instrumentation; Processor Architectures

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