On-chip instrumentation: design and debug for systems on chip

✍ Scribed by Stollon, Neal

• Publisher: Springer
• Year: 2010;2011
• Tongue: English
• Leaves: 246
• Category: Library

✦ Synopsis

This book provides an in-depth overview of on chip instrumentation technologies and various approaches taken in adding instrumentation to System on Chip (ASIC, ASSP, FPGA, etc.) design that are collectively becoming known as Design for Debug (DfD). On chip instruments are hardware based blocks that are added to a design for the specific purpose and improving the visibility of internal or embedded portions of the design (specific instruction flow in a processor, bus transaction in an on chip bus as examples) to improve the analysis or optimization capabilities for a SoC. DfD is the methodology and infrastructure that surrounds the instrumentation. Coverage includes specific design examples and discussion of implementations and DfD tradeoffs in a decision to design or select instrumentation or SoC that include instrumentation. Although the focus will be on hardware implementations, software and tools will be discussed in some detail.

✦ Table of Contents

Cover......Page 1
15.2 Toshiba EJTAG Instructions and Registers......Page 3
15.5 Break Functions......Page 7
14.5 Multicore Break Switch......Page 11
Front Matter......Page 2
13.2 ETM9 Registers......Page 4
14.2 Debug Transactor: RUN Control Bus Master......Page 6
14.3.1 BCU Level 1 (Bus-Observer Unit on the System Bus)......Page 9
14.4 RW Mode and Communication Mode......Page 10
15.4 Processor Debug Instructions and CP0 Registers......Page 5
15.6 Output by PC Trace......Page 8
12.6 TCtrace IF......Page 15
11.4 Multicore Nexus Debug Approaches......Page 17
1.1 The Need for On-Chip Debug......Page 12
1.2 Instrument- (**in-silicon) and EDA- (Presilicon) Based Verification......Page 14
12.7 PDTRACE Operations......Page 16
11.4.1 Input Tool-to-Target Messages......Page 19
11.4.2 Output Target-to-Tool Messages......Page 20
11.5 Nexus Product Implementations......Page 21
1.4 Instrumentation-Based Debug Infrastructure......Page 22
10.5.8 Security Debug Interface......Page 23
12.5 PDtrace External Interface......Page 13
1.3 SoC Debug Requirements......Page 18
11.6 Summary......Page 25
2.1 Trace and Event Triggering......Page 27
2.2 External Interfaces for On-Chip Instrumentation......Page 28
2.3 Performance Analysis Using On-Chip Instrumentation......Page 29
2.4 On-Chip Logic and Bus Analysis......Page 30
2.5.1 Trace Monitoring and Interfaces......Page 32
2.5.2 Bus Logic Monitoring......Page 33
2.5.3 Real-Time Data Exchange......Page 35
2.6 Multiprocessor Debug......Page 36
Chapter 3: JTAG Use in Debug......Page 41
3.1 JTAG Pins......Page 42
3.2 Test Access Port......Page 45
3.3 JTAG Registers......Page 48
3.4 JTAG Instructions......Page 49
3.5 Boundary-Scan Description Language......Page 50
3.6 The Road to JTAG: Historical Debug Approaches......Page 55
3.6.1 Background Debug Mode......Page 57
Chapter 4: Processor System Debug......Page 59
4.1 A Processor Debug Instrument Implementation......Page 62
4.2 Processor Trace Compression......Page 65
4.3 Hunting Code Errors with Self-Trace......Page 69
Chapter 5: An On-Chip Debug System......Page 71
5.1 OCDS Features......Page 72
5.1.1 Debug Events......Page 74
5.1.3 Debug Registers......Page 75
5.2.2 Communication Mode Instructions......Page 76
5.2.5 High-Level Synchronization......Page 77
5.3.2 Instruction Pointer Register......Page 78
5.3.3 Hardware Trigger Comparison Registers......Page 79
5.4 OCDS JTAG Access......Page 80
5.5.1 Error Protection......Page 82
5.6 OCDS JTAG I/O Instructions......Page 84
5.7 OCDS JTAG Registers......Page 86
5.8 Hardware Triggers......Page 87
5.8.1 Structure of a Noninterruptible Monitor Routine......Page 89
5.8.3 Debug Event Control Registers......Page 90
5.9 Additional Features......Page 91
5.9.1 System Security......Page 92
5.9.2 Reset from the JTAG Side......Page 93
6.1 On-Chip Buses......Page 94
6.2.1 SoC Interconnect Complexities......Page 96
6.3 Bus-Level Integration......Page 99
6.3.3 Slave Monitoring......Page 100
6.4 Internal and External Alternatives for Bus Trace......Page 101
6.5 Programmable Bus Performance Monitoring......Page 102
6.6 Bus Performance Monitoring......Page 103
6.7 On-Chip and Off-Chip Analysis......Page 107
6.8 Request Response Trace Bus Analysis......Page 110
6.8.1 RRT Operations......Page 112
6.8.2 RRT Implementation......Page 113
Chapter 7: Multiprocessor Debugging......Page 117
7.2 HyperDebug Distributed Cross-Triggering......Page 118
7.2.1 HyperDebug Controller......Page 120
7.2.2 Typical HyperDebug Implementation......Page 121
7.3 Multicore Synchronization Triggering and Global Actions......Page 123
Chapter 8: IEEE 1149.7: cJTAG/aJTAG......Page 124
8.1 Test and Debug Views of 1149.7......Page 125
8.2 Key T0–T5 Class Functions......Page 127
8.3 MIPI Use of 1149.7......Page 136
8.3.1 MIPI System Trace Module......Page 137
8.4 Nexus Use of 1149.7......Page 139
8.4.1 IEEE 1149.7/Nexus Integration......Page 141
Chapter 9: IEEE P1687 – IJTAG......Page 143
9.1 Overlap Zones and Gateway Elements......Page 145
9.2 Classes of P1687 Instruments......Page 147
9.3 IEEE 1500 Instruments......Page 149
Chapter 10: OCP IP Debug Interfaces......Page 151
10.1 OCP Multicore Debug......Page 152
10.2 OCP Debug Features......Page 155
10.3.1 Pure Software Debugging......Page 156
10.3.3 System-on-Chip Debugging......Page 157
10.4 Debug Components and IP Interfaces......Page 158
10.5.1 Core Debug Socket Interfaces......Page 160
10.5.2 Cross-Triggering Socket Interfaces......Page 163
10.5.3 OCP Synchronized Run Control......Page 167
10.5.4 OCP Traffic-Monitoring and Trace Interfaces......Page 168
10.5.5 Performance Monitoring......Page 170
10.5.6 System Timestamping......Page 171
10.5.7 Power Management Monitoring......Page 172
10.5.8 Security Debug Interface......Page 173
Chapter 11: Nexus IEEE 5001......Page 174
11.1 Nexus Implementation Classes......Page 176
11.2 Nexus Message Architecture......Page 177
11.2.1 Nexus TCODEs......Page 179
11.2.2 Nexus Registers......Page 183
11.3.1 Nexus JTAG Access......Page 185
11.3.2 NEXUS AUX Interfaces......Page 186
11.4 Multicore Nexus Debug Approaches......Page 190
11.4.1 Input Tool-to-Target Messages......Page 192
11.4.2 Output Target-to-Tool Messages......Page 193
11.5 Nexus Product Implementations......Page 194
11.6 Summary......Page 198
Chapter 12: MIPS EJTAG......Page 199
12.1 EJTAG Instructions and Registers......Page 201
12.2 PC Sampling......Page 203
12.3.1 Trace Output Formats......Page 204
12.3.2 Trace Control Block Registers......Page 208
12.4 TCB Trigger Logic Overview......Page 210
12.5 PDtrace External Interface......Page 211
12.6 TCtrace IF......Page 213
12.7 PDTRACE Operations......Page 214
13.1 ETM Signals......Page 216
13.1.1 External Signals......Page 217
13.2 ETM9 Registers......Page 219
13.3 Trace Interface......Page 221
Chapter 14: Infineon Multicore Debug Solution......Page 222
14.1 MCDS Trace Protocol Definition......Page 224
14.1.1 Data Trace......Page 226
14.2 Debug Transactor: RUN Control Bus Master......Page 227
14.3 MCDS Run Control: On-Chip Debug Support......Page 228
14.3.1 BCU Level 1 (Bus-Observer Unit on the System Bus)......Page 230
14.3.2 Concurrent Debugging in Level 3 MCDS (Two-Channel Tracing)......Page 231
14.5 Multicore Break Switch......Page 232
Chapter 15: EJTAG and Trace in Toshiba TX Cores......Page 234
15.1 Processor Access Overview......Page 235
15.2 Toshiba EJTAG Instructions and Registers......Page 236
15.4 Processor Debug Instructions and CP0 Registers......Page 238
15.5 Break Functions......Page 240
15.6 Output by PC Trace......Page 241
b978-0-387-78701_4......Page 243