Preface
Acknowledgments
Abstract
Contents
List of Abbreviations
List of Figures
List of Tables
About the Authors
1 Effects of Transient Faults in Integrated Circuits
1.1 Context of Transient Faults for Integrated Circuit Reliability and Security
1.2 Transient Faults Induced by Environmental Perturbations
1.3 Transient Faults Induced by Intentional Perturbations
1.4 Electrical-Level Effects of Transient Faults in Integrated Circuits
1.5 Logical-Level Effects of Transient Faults in Integrated Circuit Systems
1.5.1 Harmful Effects of Transient Faults on SynchronousCircuits
1.5.2 Harmful Effects of Transient Faults on QDI Asynchronous Circuits
1.5.3 Harmless Effects of Transient Faults
1.5.4 Failures: The Effects of Soft Errors
1.5.5 Harmful Effects of Long-Duration Transient Faults
1.5.6 Harmful Effects of Multiple Transient Faults
1.6 Conclusions
2 Effectiveness of Hardware-Level Techniques in Detecting Transient Faults
2.1 Techniques for Concurrent Error Detection
2.1.1 Spatial Redundancy
2.1.2 Temporal Redundancy
2.1.3 Transition Detector-Based Techniques
2.1.4 Built-In Current Sensors
2.2 Method for Evaluation of Concurrent Error Detection Techniques
2.2.1 Analysis of Injected Transient-Fault Effects
2.2.2 Profiles of Injected Transient Faults
2.2.3 Evaluation Metrics
2.3 Comparative Analysis of Techniques for Detection of Transient Faults
2.3.1 Description of Simulation Experiments
2.3.2 Comparative Analysis for Scenario 5
2.3.3 Global Comparative Analysis
2.4 Conclusions
3 Architectures of Body Built-In Current Sensors for Detection of Transient Faults
3.1 Fundamentals and History of Built-In Current Sensors
3.2 State-of-the-Art Architectures of Body Built-In Current Sensors
3.2.1 Single BBICS Architectures
3.2.2 BBICS Architectures of Neto et al.
3.2.3 BBICS Architectures of Zhang et al.
3.2.4 Modular BBICS Architectures
3.2.5 Dynamic BBICS Architectures of Simionovski and Wirth
3.2.6 Optimal Dynamic BBICS Architectures
3.3 Reference Sensitivity of a Flip-Flop in Detecting Transient Faults
3.3.1 Experiments for Analyzing the Sensitivity of a Flip-Flop in Detecting Transient Faults
3.3.2 Results and Analysis of the Sensitivity of a Flip-Flop in Detecting Transient Faults
3.4 Analysis and Comparison of Sensor Sensitivities in Detecting Transient Faults
3.4.1 Experiments for Sizing Sensor Architectures
3.4.2 Experiments for Analyzing the Sensitivities of Sensor Architectures in Detecting Transient Faults
3.4.3 Comparative Analysis of Sensor Sensitivities in Detecting Transient Faults
3.4.4 Influence of Process and Temperature Variations on the Sensor Detection Sensitivity
3.4.5 Influence of the Monitored Subcircuit Area on the Sensor Detection Sensitivity
3.5 Estimation of Sensor Area Overhead Imposed on the Monitored Subcircuit Area
3.6 Analysis of Sensor Sensitivity in Detecting Multiple (Simultaneous) Transient Faults
3.6.1 Modeling Transient Faults According to Nominal VDD of the Case-Study Subcircuit
3.6.2 Defining Scenarios of Multiple Transient Faults in the Case-Study Subcircuit
3.6.3 Finding the Critical Profiles of Transient Faults
3.6.4 Simulation Experiments and Results
Minimum Current Fall and Rise Time
Minimum Detectable Injected Charges
3.7 Conclusions
4 Enhancing the Design of Body Built-In Sensor Architectures
4.1 Concept of the Modular Body Built-In Sensor
4.1.1 Origination of the Approach
4.1.2 Basic Structure
4.1.3 Mode of Operation
4.1.4 Sizing
4.2 Strategies for Improving Body Built-In Sensors
4.2.1 Adjustable Gate Voltage on Sensing Transistor
4.2.2 Threshold Voltage Modification via Body-Biasing
4.2.3 Stack Forcing
4.2.4 Sizing and Voltage Levels
4.3 Simulation Results
4.3.1 Standard mBBICS
Simulation Environment
Nominal Case
Robustness Analysis
Impact of Technology Scaling
4.3.2 Improved mBBICS
Test Environment
Characterization
Robustness Analysis
4.3.3 Comparison to Other Works
4.4 Conclusions
5 Noise Robustness of Body Built-In Sensors
5.1 Motivation
5.2 Noise Sources
5.2.1 Device Noise
5.2.2 Switching Noise
5.2.3 Substrate Noise Coupling
5.3 Modeling
5.3.1 Substrate Modeling
5.3.2 Noise Modeling
5.4 Analysis Environment
5.4.1 Sensor Circuits
5.4.2 Digital Test Circuits
5.4.3 Influence of Simulation Time
5.5 Results
5.5.1 Exploration of Required Noise Level for SensorActivation
5.5.2 Distance Analysis
5.5.3 Noise Generation by Digital Test Circuit
5.5.4 Number of Monitored Transistors
5.5.5 Exposure Time
5.6 Conclusions
6 Body Built-In Cells for Detecting Transient Faults and Adaptively Biasing Subcircuits
6.1 Adaptive Body Biasing Strategy for Tuning Power and Delay of Subcircuits
6.1.1 FD-SOI Technology
6.1.2 State-of-the-Art Level Shifter (LS) Architectures
6.2 Architecture of Body Built-In Cells for Detecting Faults and Biasing Subcircuits
6.2.1 LS Structure
6.2.2 BBICS-Based Structure
6.3 Effectiveness of Body Built-In Cells in Detecting Faults and Biasing Subcircuits
6.3.1 Body Biasing Effectiveness
6.3.2 Sensitivity in Detecting Transient Faults
6.4 Conclusions
7 Automatic Integration of Body Built-In Sensors into Digital Design Flows
7.1 Automatic Layout Integration
7.1.1 Standard Cell Design
7.1.2 Automatic Flow for Sensor Insertion
7.1.3 Clustering and Head Insertion Strategies
Addition of Double Head Cells
Mixed Addition of Double and Single Head Cells
Addition of Tail Cells and Final Routing
7.1.4 Exemplary Cell Library
Standard Cells
mBBICS Cells
mBBICS Sensibility Estimation
7.1.5 Exploration
Environment
Comparison of Head Insertion Strategies
Impact of Benchmark Circuit
Maximum Load
Aspect Ratio
7.2 Light-Weight Rollback Processor Using Body Built-In Sensors
7.2.1 Processor Architecture
Basic RISC Processor
RISC Processor with Rollback
7.2.2 Results
7.3 Conclusions
8 Body Built-In Sensors for Testing Integrated Circuit Systems for Hardware Trojans
8.1 Testing Techniques for Detection of Hardware Trojans
8.2 Body Built-in Sensor-Based Testing Technique for Detection of Hardware Trojans
8.2.1 Injection of Current Pulses into Body Terminals of DUTT Subcircuits
8.2.2 Monitoring of Current Sensors Built in DUTTSubcircuits
8.2.3 Compilation of Signatures Collected From Subcircuit Substrate by the Sensors
8.2.4 Statistical Analysis for Identifying DUTT Subcircuits Infected with HT
8.3 Effectiveness of Body Built-in Sensors in Detecting Hardware Trojans
8.3.1 Description of Simulation Experiments
8.3.2 Target HT Implanted in DUTTs
8.3.3 Case-Study DUTTs and Analyses of Simulation Results
8.3.4 Sensor Area Overhead Imposed on the DUTT Area and Number of DUTT Samples Required for Detectinga HT
8.4 Conclusions
References
Index