On-Chip Current Sensors for Reliable, Se
β Rodrigo Possamai Bastos, Frank Sill Torres
π Library
π
2020
π Springer
π English
β¦ LIBER β¦
π
Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
β Scribed by Sung Kyu Lim (auth.)
- Publisher
- Springer-Verlag New York
- Year
- 2013
- Tongue
- English
- Leaves
- 571
- Edition
- 1
- Category
- Library
β¬ Acquire This Volume
No coin nor oath required. For personal study only.
β¦ Synopsis
This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous βmanufacturing-readyβ GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.
β¦ Table of Contents
Front Matter....Pages i-xxviii
Front Matter....Pages 1-1
Regular Versus Irregular TSV Placement for 3D IC....Pages 3-40
Steiner Routing for 3D IC....Pages 41-73
Buffer Insertion for 3D IC....Pages 75-97
Low Power Clock Routing for 3D IC....Pages 99-128
Power Delivery Network Design for 3D IC....Pages 129-151
3D Clock Routing for Pre-bond Testability....Pages 153-185
Front Matter....Pages 187-187
TSV-to-TSV Coupling Analysis and Optimization....Pages 189-203
TSV Current Crowding and Power Integrity....Pages 205-229
Modeling of Atomic Concentration at the Wire-to-TSV Interface....Pages 231-250
Front Matter....Pages 251-251
Multi-objective Architectural Floorplanning for 3D IC....Pages 253-283
Thermal-Aware Gate-Level Placement for 3D IC....Pages 285-308
3D IC Cooling with Micro-Fluidic Channels....Pages 309-341
Front Matter....Pages 343-343
Mechanical Reliability Analysis and Optimization for 3D ICs....Pages 345-378
Impact of Mechanical Stress on Timing Variation for 3D IC....Pages 379-414
Chip/Package Co-analysis of Mechanical Stress for 3D IC....Pages 415-441
3D Chip/Package Co-analysis of Stress-Induced Timing Variations....Pages 443-465
TSV Interfacial Crack Analysis and Optimization....Pages 467-489
Front Matter....Pages 491-491
Ultra High Density Logic Designs Using Monolithic 3D Integration....Pages 493-514
Impact of TSV Scaling on 3D IC Design Quality....Pages 515-535
3D-MAPS: 3D Massively Parallel Processor with Stacked Memory....Pages 537-560
β¦ Subjects
Circuits and Systems; Nanotechnology and Microengineering; Processor Architectures
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