𝔖 Scriptorium
✦   LIBER   ✦
πŸ“

Low Power Methodology Manual: For System-on-Chip Design (Integrated Circuits and Systems)

✍ Scribed by David Flynn, Rob Aitken, Alan Gibbons, Kaijian Shi

Publisher
Springer
Year
2007
Tongue
English
Leaves
277
Series
Integrated Circuits and Systems
Category
Library
⬇  Acquire This Volume

No coin nor oath required. For personal study only.

✦ Synopsis

β€œTools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach.”

Richard Goering, Software Editor, EE Times

β€œExcellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion.”

Sujeeth Joseph, Chief Architect - SemiconductorΒ and Systems Solutions Unit, Wipro Technologies

β€œThe LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs.”

Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc.

β€œManaging power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management.”

Nick Salter, Head of Chip Integration, CSR plc.

πŸ“œ SIMILAR VOLUMES

Low Power Methodology Manual: For System
πŸ“ Low Power Methodology Manual: For System-on-Chip Design (Integrated Circuits and Systems)
✍ David Flynn, Rob Aitken, Alan Gibbons, Kaijian Shi πŸ“‚ Library πŸ“… 2007 πŸ› Springer 🌐 English

This book provides a practical guide for engineers doing low power System-on-Chip (SoC) designs. It covers various aspects of low power design from architectural issues and design techniques to circuit design of power gating switches. In addition to providing a theoretical basis for these techniques

Low Power Methodology Manual: For System
πŸ“ Low Power Methodology Manual: For System-on-Chip Design
✍ Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, Kaijian Shi (auth.) πŸ“‚ Library πŸ“… 2007 πŸ› Springer US 🌐 English

<p><P><EM>"Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to

Sub-threshold Design for Ultra Low-Power
πŸ“ Sub-threshold Design for Ultra Low-Power Systems (Integrated Circuits and Systems)
✍ Alice Wang, Benton Highsmith Calhoun, Anantha P. Chandrakasan πŸ“‚ Library πŸ“… 2006 πŸ› Springer 🌐 English

Based on the work of MIT graduate students Alice Wang and Benton Calhoun, this book surveys the field of sub-threshold and low-voltage design and explores such aspects of sub-threshold circuit design as modeling, logic and memory circuit design. One important chapter of the book is dedicated to opti

Reuse Methodology Manual for System-on-a
πŸ“ Reuse Methodology Manual for System-on-a-Chip Designs
✍ Michael Keating, Pierre Bricaud πŸ“‚ Library πŸ“… 2002 πŸ› Springer 🌐 English

Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in an SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in