Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synt
New Data Structures and Algorithms for Logic Synthesis and Verification
โ Scribed by Luca Gaetano Amaru (auth.)
- Publisher
- Springer International Publishing
- Year
- 2017
- Tongue
- English
- Leaves
- 162
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
โฆ Synopsis
This book introduces new logic primitives for electronic design automation tools. The author approaches fundamental EDA problems from a different, unconventional perspective, in order to demonstrate the key role of rethinking EDA solutions in overcoming technological limitations of present and future technologies. The author discusses techniques that improve the efficiency of logic representation, manipulation and optimization tasks by taking advantage of majority and biconditional logic primitives. Readers will be enabled to accelerate formal methods by studying core properties of logic circuits and developing new frameworks for logic reasoning engines.
โฆ Table of Contents
Front Matter....Pages i-xvi
Introduction....Pages 1-12
Front Matter....Pages 13-13
Biconditional Logic....Pages 15-55
Majority Logic....Pages 57-102
Front Matter....Pages 103-103
Exploiting Logic Properties to Speedup SAT....Pages 105-119
Majority Normal Form Representation and Satisfiability....Pages 121-133
Improvements to the Equivalence Checking of Reversible Circuits....Pages 135-149
Conclusions....Pages 151-153
Back Matter....Pages 155-156
โฆ Subjects
Circuits and Systems;Processor Architectures;Logic Design
๐ SIMILAR VOLUMES
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synt
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Syn
<p><em>Logic Synthesis and Verification Algorithms</em> is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. <br/
Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this