Logic Synthesis and Verification Algorithms

✍ Scribed by Gary D. Hachtel, Fabio Somenzi (auth.)

Publisher: Springer US
Year: 2002
Tongue: English
Leaves: 567
Edition: 1
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.
Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.
A unique feature of this text is the large collection of solved problems.
Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

✦ Table of Contents

Introduction....Pages 5-45
A Quick Tour of Logic Synthesis with the Help of a Simple Example....Pages 47-76
Boolean Algebras....Pages 77-126
Synthesis of Two-Level Circuits....Pages 127-183
Heuristic Minimization of Two-level Circuits....Pages 185-218
Binary Decision Diagrams (BDDs)....Pages 219-254
Models of Sequential Systems....Pages 255-324
Synthesis and Verification of Finite State Machines....Pages 325-368
Finite Automata....Pages 369-403
Multi-Level Logic Synthesis....Pages 409-453
Multi-Level Minimization....Pages 455-474
Automatic Test Generation for Combinational Circuits....Pages 475-503
Technology Mapping....Pages 505-521

✦ Subjects

Circuits and Systems; Electronic and Computer Engineering; Computer-Aided Engineering (CAD, CAE) and Design; Discrete Mathematics in Computer Science; Computing Methodologies

📜 SIMILAR VOLUMES

Logic Synthesis and Verification Algorit

📁 Logic Synthesis and Verification Algorithms

✍ Hachtel G.D., Somenzi F. 📂 Library 📅 1996 🏛 Springer 🌐 English

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synt

Logic Synthesis and Verification Algorit

📁 Logic Synthesis and Verification Algorithms

✍ Hachtel G.D., Somenzi F. 📂 Library 📅 1996 🏛 Springer 🌐 English

Logic Synthesis and Verification Algorit

📁 Logic Synthesis and Verification Algorithms

✍ Gary D. Hachtel, Fabio Somenzi 📂 Library 🌐 English

New Data Structures and Algorithms for L

📁 New Data Structures and Algorithms for Logic Synthesis and Verification

✍ Luca Gaetano Amaru (auth.) 📂 Library 📅 2017 🏛 Springer International Publishing 🌐 English

<p><p>This book introduces new logic primitives for electronic design automation tools. The author approaches fundamental EDA problems from a different, unconventional perspective, in order to demonstrate the key role of rethinking EDA solutions in overcoming technological limitations of present and

Logic Synthesis and Verification

📁 Logic Synthesis and Verification

✍ Hassoun S., Sasao T. (ed.) 📂 Library 📅 2001 🏛 Springer 🌐 English

Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this

Logic synthesis and verification

📁 Logic synthesis and verification

✍ Soha Hassoun; Tsutomu Sasao 📂 Library 📅 2002 🏛 Kluwer Academic Publishers 🌐 English