With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High b
Networks on Chip
โ Scribed by Axel Jantsch, Hannu Tenhunen (auth.), Axel Jantsch, Hannu Tenhunen (eds.)
- Publisher
- Springer US
- Year
- 2004
- Tongue
- English
- Leaves
- 303
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
โฆ Synopsis
As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.
โฆ Table of Contents
Will Networks on Chip Close the Productivity Gap?....Pages 3-18
A Design Methodology for NOC-Based Systems....Pages 19-38
Mapping Concurrent Applications onto Architectural Platforms....Pages 39-59
Guaranteeing the Quality of Services in Networks on Chip....Pages 61-82
On Packet Switched Networks for On-Chip Communication....Pages 85-106
Energy-Reliability trade-Off for NoCs....Pages 107-129
Testing Strategies for Networks on Chip....Pages 131-152
Clocking Strategies for Networks-on-Chip....Pages 153-172
A Parallel Computer as a NOC Region....Pages 173-192
An IP-Based On-Chip Packet-Switched Network....Pages 193-213
Beyond the Von Neumann Machine....Pages 217-238
NoC Application Programming Interfaces....Pages 239-260
Multi-Level Software Validation for NoC....Pages 261-279
Software for Multiprocessor Networks on Chip....Pages 281-303
โฆ Subjects
Processor Architectures; Computer-Aided Engineering (CAD, CAE) and Design; Operating Systems; Special Purpose and Application-Based Systems
๐ SIMILAR VOLUMES
Networks on Chip presents a variety of topics, problems and approaches with the common theme to systematically organize the on-chip communication in the form of a regular, shared communication network on chip, an NoC for short.As the number of processor cores and IP blocks integrated on a single chi
<p><p>This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet r
<p><p>This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet r
<p><p>This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet r