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Multiple-output parity bit signature for exhaustive testing

โœ Scribed by Wen-Ben Jone; Sunil R. Das

Book ID
104636964
Publisher
Springer US
Year
1990
Tongue
English
Weight
281 KB
Volume
1
Category
Article
ISSN
0923-8174

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โœฆ Synopsis

In this article we propose a multiple-output parity bit signature generation method for exhaustive testing of VLSI circuits. Given a multiple-output combinational circuit, a parity bit signature is generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method preserves all the desirable properties of the conventional single-output circuits response analyzers and can be readily implemented using the current VLSI technology.

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โœ Sungju Park; Sheldon B. Akers ๐Ÿ“‚ Article ๐Ÿ“… 1992 ๐Ÿ› Springer US ๐ŸŒ English โš– 760 KB

Parity bit checking and pseudo-exhaustive testing are two design techniques which have been widely discussed in the BIST literature but have seldom been employed in practice because of the exponential nature of the processes involved. In this paper we describe several procedures designed to avoid th