In this article we propose a multiple-output parity bit signature generation method for exhaustive testing of VLSI circuits. Given a multiple-output combinational circuit, a parity bit signature is generated by first EXORing all the outputs to produce a new output function and then feeding this resu
โฆ LIBER โฆ
A parity bit signature for exhaustive testing
โ Scribed by Akers, S.B.
- Book ID
- 119777852
- Publisher
- IEEE
- Year
- 1988
- Tongue
- English
- Weight
- 593 KB
- Volume
- 7
- Category
- Article
- ISSN
- 0278-0070
- DOI
- 10.1109/43.3166
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