Multi-level factorisation technique for pass transistor logic
โ Scribed by Jaekel, A.; Bandyopadhyay, S.; Jullien, G.A.
- Book ID
- 114447637
- Publisher
- The Institution of Electrical Engineers
- Year
- 1998
- Tongue
- English
- Weight
- 740 KB
- Volume
- 145
- Category
- Article
- ISSN
- 1350-2409
No coin nor oath required. For personal study only.
๐ SIMILAR VOLUMES
This paper presents a review of differential and pass-transistor logic used in today's high performance systems. Various circuit and logic design styles used in contemporary high performance processors have been reviewed. The new logic is advantageous over standard CMOS in terms of performance and v
Performance evaluation of a two-level carry-skip adder using complementary pass-transistor logic (CPL) is presented in this paper. The adder is compared with a fulI-CMOS version of the two-level carry-skip architecture, with a carry-lookahead adder automatically generated with ALLIANCE CAD tools and