Modelling and design considerations on CML gates under high-current effects

✍ Scribed by M. Alioto; G. Palumbo

• Book ID: 102127342
• Publisher: John Wiley and Sons
• Year: 2005
• Tongue: English
• Weight: 162 KB
• Volume: 33
• Category: Article
• ISSN: 0098-9886
• DOI: 10.1002/cta.333

✦ Synopsis

In this paper, the e ect of the transit time degradation of bipolar transistors on the power-delay tradeo in CML gates and their design is dealt with. A delay model which accounts for the transit time increase due to the high bias current values used in high-speed applications is derived by generalizing an approach previously proposed by the same authors (IEEE Trans.