✦ LIBER ✦

Modeling of MOS scaling with emphasis on gate tunneling and source/drain resistance

✍ Scribed by Chang-Hoon Choi; Zhiping Yu; Robert W. Dutton

Book ID: 102619802
Publisher: Elsevier Science
Year: 2000
Tongue: English
Weight: 393 KB
Volume: 27
Category: Article
ISSN: 0749-6036
DOI: 10.1006/spmi.1999.0799

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✦ Synopsis

Two critical aspects of the MOS scaling towards sub-100 nm gate length are addressed: the gate tunneling and capacitance modeling, and optimization of shallow source/drain (S/D) extension junction to minimize the series resistance. Both advanced physics (quantum mechanics or QM) and practical solution (circuit simulation) are used to tackle the modeling approach. Good results have been obtained compared to available experimental data, validating the hierarchical methodology used in this paper. A hybrid, semi-analytical QM model for channel carrier profile and an accurate direct tunneling model have been developed. An nMOS transistor with effective channel length of 0.08 micron has been analyzed to demonstrate the methodology proposed.

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