✦ LIBER ✦

Modeling of interconnect capacitance, delay, and crosstalk in VLSI

✍ Scribed by Shyh-Chyi Wong, ; Gwo-Yann Lee, ; Dye-Jyun Ma,

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Minimization of delay and crosstalk in h

✍ Zhang, Q.-J.; Lum, S.; Nakhla, M.S. 📂 Article 📅 1992 🏛 IEEE 🌐 English ⚖ 791 KB

Closed-form expressions for interconnect

✍ Sakurai, T. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 564 KB

A multilevel parasitic interconnect capa

✍ Lee, M. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 107 KB

Crosstalk model and estimation formula f

✍ Liu Ling-zhi; Gong Shu; Rong Meng-tian 📂 Article 📅 2002 🏛 Wuhan University 🌐 English ⚖ 334 KB

Delay and crosstalk simulation of high-s

✍ Xie, D.H.; Nakhla, M. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 825 KB

Efficient Delay and Crosstalk Modeling o

✍ Roy, S.; Dounavis, A. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 277 KB