✦ LIBER ✦
A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation
✍ Scribed by Lee, M.
- Book ID
- 119775044
- Publisher
- IEEE
- Year
- 1998
- Tongue
- English
- Weight
- 107 KB
- Volume
- 33
- Category
- Article
- ISSN
- 0018-9200
- DOI
- 10.1109/4.663574
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