Mobile 3D Graphics SoC: From Algorithm to Chip

✍ Scribed by Hoi-Jun Yoo, Jeong-Ho Woo, Ju-Ho Sohn, Byeong-Gyu Nam

• Publisher: Wiley
• Year: 2010
• Tongue: English
• Leaves: 342
• Category: Library

✦ Synopsis

The first book to explain the principals behind mobile 3D hardware implementation, helping readers understand advanced algorithms, produce low-cost, low-power SoCs, or become familiar with embedded systems

As mobile broadcasting and entertainment applications evolve, there is increasing interest in 3D graphics within the field of mobile electronics, particularly for handheld devices. In Mobile 3D Graphics SoC , Yoo provides a comprehensive understanding of the algorithms of mobile 3D graphics and their real chip implementation methods. 3D graphics SoC (System on a Chip) architecture and its interaction with embedded system software are explained with numerous examples. Yoo divides the book into three sections: general methodology of low power SoC, design of low power 3D graphics SoC, and silicon implementation of 3D graphics SoCs and their application to mobile electronics. Full examples are presented at various levels such as system level design and circuit level optimization along with design technology. Yoo incorporates many real chip examples, including many commercial 3D graphics chips, and provides cross-comparisons of various architectures and their performance. Furthermore, while advanced 3D graphics techniques are well understood and supported by industry standards, this is less true in the emerging mobile applications and games market. This book redresses this imbalance, providing an in-depth look at the new OpenGL ES (The Standard for Embedded Accelerated 3D Graphics), and shows what these new embedded systems graphics libraries can provide for 3D graphics and games developers.

✦ Table of Contents

MOBILE 3D GRAPHICS SoC: From Algorithm to Chip......Page 1
Contents......Page 7
Preface......Page 11
1.1 Mobile 3D Graphics......Page 13
1.2.1 Mobile Computing Power......Page 15
1.2.3 Design Challenges......Page 17
1.3 Introduction to SoC Design......Page 18
1.4 About this Book......Page 19
2.1.1 Platform and Set-based Design......Page 21
2.1.2 Modeling: Memory and Operations......Page 26
2.2.1 Reference Machine and API......Page 30
2.2.2 Communication Architecture Design......Page 34
2.2.3 System Analysis......Page 37
2.3.2 Architecture-level Low-power Design......Page 39
2.4 Network-on-Chip based SoC......Page 40
2.4.1 Network-on-Chip Basics......Page 41
2.4.2 NoC Design Considerations......Page 53
2.4.3 Case Studies of Chip Implementation......Page 60
3 Introduction to 3D Graphics......Page 79
3.1.2 The Geometry Stage......Page 80
3.1.3 The Rendering Stage......Page 86
3.2.1 Programmable Graphics Pipeline......Page 90
3.2.2 Shader Models......Page 93
4.1 Principles of Mobile 3D Graphics......Page 97
4.1.1 Application Challenges......Page 98
4.1.2 Design Principles......Page 99
4.2.1 KAIST MobileGL......Page 103
4.2.2 Khronos OpenGL-ES......Page 105
4.2.3 Microsoft’s Direct3D-Mobile......Page 107
4.3 Summary and Future Directions......Page 108
5 Mobile 3D Graphics SoC......Page 111
5.1 Low-power Rendering Processor......Page 112
5.1.1 Early Depth Test......Page 113
5.1.2 Logarithmic Datapaths......Page 114
5.1.3 Low-power Texture Unit......Page 116
5.1.4 Tile-based Rendering......Page 118
5.1.5 Texture Compression......Page 119
5.1.6 Texture Filtering and Anti-aliasing......Page 121
5.2.1 Vertex Cache......Page 122
5.2.2 Low-power Register File......Page 123
5.2.3 Mobile Unified Shader......Page 125
6.1 KAIST RAMP Architecture......Page 131
6.1.1 RAMP-IV......Page 132
6.1.2 RAMP-V......Page 135
6.1.3 RAMP-VI......Page 139
6.1.4 RAMP-VII......Page 144
6.2.1 nVidia Mobile GPU – SC10 and Tegra......Page 151
6.2.2 Sony PSP......Page 155
6.2.3 Imagination Technology MBX/SGX......Page 156
7.1 Target System Architecture......Page 161
7.3 Block Diagram of the Rasterizer......Page 162
7.4 Instruction Set Architecture (ISA)......Page 163
7.5.1 Rasterization Top Block......Page 166
7.5.3 Main Controller Design......Page 168
7.5.4 Rasterization Core Unit......Page 170
8.1 Game and Mapping Applications Involving Networking......Page 307
8.2 Moves Towards More User-centered Applications......Page 308
8.3 Final Remarks......Page 309
A.1 Introduction to Verilog Design......Page 311
A.2.3 Gate Level......Page 312
A.3 Design Flow......Page 313
A.3.2 High-level Design......Page 314
A.3.4 RTL Coding......Page 315
A.3.6 Synthesis......Page 316
A.4 Verilog Syntax......Page 317
A.4.1 Modules......Page 318
A.4.2 Logic Values and Numbers......Page 319
A.4.3 Data Types......Page 320
A.4.4 Operators......Page 321
A.4.5 Assignment......Page 323
A.4.7 Expressions......Page 324
A.4.8 Instantiation......Page 326
A.4.9 Miscellaneous......Page 328
A.5 Example of Four-bit Adder with Zero Detection......Page 330
A.6 Synthesis Scripts......Page 332
Glossaries......Page 335
Index......Page 337
Colour Plate......Page 341